Verilog / VHDL Jobs

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  • Fixed-Price – Est. Budget: $85.00 Posted
    The Basic aim of the project is to Design and implement a Hardware Firewall which would enable us to secure our Network.The hardware firewall will be packet filtering to examine the header of a packet to determine its source and desitination. The information will be compared to a set of predefined or user-created rules that determines whether the packet is to be forwarded or dropped. this has to be done using Xilinx Virtex-5 FPGA board using Verilog HDL
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