Verilog / VHDL Jobs

30 were found based on your criteria

  • Fixed-Price – Est. Budget: $85.00 Posted
    The Basic aim of the project is to Design and implement a Hardware Firewall which would enable us to secure our Network.The hardware firewall will be packet filtering to examine the header of a packet to determine its source and desitination. The information will be compared to a set of predefined or user-created rules that determines whether the packet is to be forwarded or dropped. this has to be done using Xilinx Virtex-5 FPGA board using Verilog HDL
  • Fixed-Price – Est. Budget: $100.00 Posted
    Goal of the proposed iris recognition is to recognize human identity througb the textural characteristics of one's iris muscular patterns. Even though eye color is dependent on heredity, in contrast to this, iris is independent and uncorrelated even for twins. Out of various biometrics such as f'mger and band geometry, face, ear and voice recognition, iris recognition has been acknowledged as one of the most accurate biometric modalities because of its high recognition rate. In this proposed iris ...
  • Fixed-Price – Est. Budget: $60.00 Posted
    https://wiki.eecs.yorku.ca/course_archive/2014-15/F/2021/_media/labm.pdf
  • Fixed-Price – Est. Budget: $400.00 Posted
    Detailed Description is in the file attached. I want to secure the data and other critical security parameters present on FPGA. If an unauthorised user tries to temper the FPGA, all Critical Security parameters should be secured. Different methods are mentioned in the document like reset, ramoverwrite, etc. I might need you to implement 1 or 2 methods rather then all the methods mentioned in the document attached.
  • Fixed-Price – Est. Budget: $20.00 Posted
    design and comparison of 8bit risk and cisc processors. design a verilog code for risk and cisc processors running a set of 12 instructions and compare their timing analysis, their power dissipation and area. The instructions to be used are : add, addi, sub, subj, addc, subc, rol, ror, load wrd, store word, jump, subroutine, xor, xnor
  • Fixed-Price – Est. Budget: $5,000.00 Posted
    This job consists in the implementation of a scrypt for litecoin mining in a structured ASIC processor. The candidate should describe his/her experience with structured ASIC and availability for developing on his/her end. It is also necessary to give an estimate of average timeframe for the complete implementation starting from an existing FPGA code.
  • Fixed-Price – Est. Budget: $150.00 Posted
    I need an expert in Altera software implementation to simulate the speed of an algorithm running on DE0 board and the fatest you have experience.
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