Verilog / VHDL Jobs

75 were found based on your criteria

  • Fixed-Price – Est. Budget: $25.00 Posted
    Hello Guys, Please find the Doc and diagram attached below which I had given: 1. A FIFO queue is a special purpose register file “n” words deep and “m” bits wide has the following input and output a. Inputs : clock, push_data(1 bit), pop_data(1 bit), data_in(32 bit), address(16 bit), reset b. Outputs: full(1 bit), empty(1 bit), data_out(32 bit), The operation is as follows: When push_data is asserted, new data at the input is get ...
  • Fixed-Price – Est. Budget: $500.00 Posted
    I need the JPEG2000 Tier 2 code developing for use in an FPGA. I also need the rate control. I have the Tier 1 part developed. So I need the output from this block interfacing to Tier 2.
  • Fixed-Price – Est. Budget: $2,000.00 Posted
    FPGA Signal Synthesis to Quad TI DACs Using Vivado and LabVIEW on the VC707 Using the VC707 Xilinx Virtex 7 prototyping platform and the TI DAC3484EVM connected via TI’s FMC to DAC adapter, create working signal synthesis code in VHDL or Verilog. You must use the Vivado Platform, combined with NI’s LabVIEW software to control the signal synthesis. The working code must be verified as functional at our site with the equivalent hardware/software platform. The selected candidate ...
  • Fixed-Price – Est. Budget: $60.00 Posted
    https://wiki.eecs.yorku.ca/course_archive/2014-15/F/2021/_media/labn.pdf LabM10 from the previous lab is needed for this assignment https://wiki.eecs.yorku.ca/course_archive/2014-15/F/2021/_media/labm.pdf I have LabM1-LabM6 completed, will send if needed.
  • Fixed-Price – Est. Budget: $60.00 Posted
    https://wiki.eecs.yorku.ca/course_archive/2014-15/F/2021/_media/labm.pdf
  • Fixed-Price – Est. Budget: $400.00 Posted
    Hello I require a verilog code for detecting objects in HD video using Adaboost as algorithm. Video from the camera will input into FPGA board (any board) and detected objects will be output through VGA port or HDMI port. I will give extra bucks if the code has any one of following characteristics: 1. Slice LUTs less than 25,800 2. Slice register less than 23,700 3. Block RAM less than 24 The system should be able to detect ...
  • Fixed-Price – Est. Budget: $5,000.00 Posted
    • Work on Zynq 7000 series SoCs and boards based on that (Zedboard, Parallella, MicroZed); • Implementation, testing and optimization of FPGA modules for various algorithms and protocols throughout the project; • Good understanding and experience of all Xilinx tools, design suites, Zynq architecture, Verilog and/or VHDL; • Experience with partial reconfiguration; • Good understanding and experience with UNIX operating system; • Experience/knowledge on ARM architecture and ARM development studio;
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