Verilog Jobs

16 were found based on your criteria

  • Fixed-Price – Est. Budget: $150.00 Posted
    I need an expert in Altera software implementation to simulate the speed of an algorithm running on DE0 board and the fatest you have experience.
  • Fixed-Price – Est. Budget: $70.00 Posted
    http://ecee.colorado.edu/~ecen2350/problems/project03.html I wont be able to pay untill 26th December.
  • Fixed-Price – Est. Budget: $2,000.00 Posted
    DfR Solutions, LLC is seeking a talented, self-driven and motivated software engineer/FPGA designer/engineer to support the development of a test to prove out the reliability of space-bound FPGA designs. The applicant must be proficient in Xilinx Vivado and ISE suites (specifically ISE WebPack design software from Xilinx) and technically confident to develop code while working independently. The objective of this contract is to develop an FPGA level software routine similar to an iterative Built-In-Self-Test (BIST) to be used ...
  • Hourly – Less than 1 month – 10-30 hrs/week – Posted
    Looking for an FPGA expert, with knowledge in XILINX tools and synthesis. Knowledge preferd in ZYNQ and xilinx tools such as XPS and Plan ahead. Language: VERILOG looking for someone who can start right away! English level should be good!
  • Fixed-Price – Est. Budget: $50.00 Posted
    I have Implemented the single cycle MIPS 32 CPU. I have attached my project and its description as an attachment. I want to convert it into Verilog MIPS Pipelined Datapath alongwith the instructions included in my project as well as JMP and BNE instructions.
  • Fixed-Price – Est. Budget: $500.00 Posted
    I am looking for an FPGA designer for an exciting task. -The designer must have experience in XILLINX FPGAS -Experience with ZYNQ or ZEDBOARD is a big + -Experience in embedded systems, ARM, RTOS More details will be handed to chosen applicants Thank you..
  • Hourly – Less than 1 month – Less than 10 hrs/week – Posted
    My team and I are developing a brand new FPGA. We need to know what kind of circuit designs we need to implement so that we can program the device easily. Altera Quartus II seems like a great software package for this type of chip programming. There are two major methods used by Quatus to program an FPGA: JTAG programming (volatile) and Active Serial programming (non-volatile). We need to know more details about these methods. First, describe the method of ...
  • Fixed-Price – Est. Budget: $60.00 Posted
    2 Directions design an MMP circuit showing the implemention of the two's complement multiplication algorithm from Project 1. No pseudo-instructions are al-lowed in the implementation. With the exception of the Control Unit, you may use only the com-ponents provided in the TinyCad symbol library|\gen_CompArch.TCLib". Initialize the Data Memory with the ASCII codes representing the multiplier and multiplicand numerals. Finally, design and simulate the MMP using hardware description language. Assume that the address of the rst instruction in ...
  • Fixed-Price – Est. Budget: $400.00 Posted
    This project contains the top level module DE2_70_TOP.v, and several reusable cores developed by Altera: a VGA controller core Ctrl.v for synchronization signals. a reset module for resetting the PLL, and an Altera Megawizard components VGA_Audio_PLL.v. Go through the files to gain basic understandings. 2. Modify file DE2-70-TOP.v so that it controls the VGA to display colours according to the settings of the iSWs, especially: Red colour signal is controlled by the [17:12] bits of ...
  • Hourly – Less than 1 month – 10-30 hrs/week – Posted
    Using http://sourceforge.net/projects/v2kparse/ , write a program to extract information from verilog files and present it as key=value pairs. Information needed 1) Module name 2) Number of ports 3) Number of input ports 4) Number of output ports 5) Number of bi-dir ports 6) Number of instances in the module 7) Number of nets in the module The program must be able to handle structural as well as RTL verilog
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