Verilog / VHDL Jobs

9 were found based on your criteria

  • Fixed-Price – Est. Budget: $60.00 Posted
    https://wiki.eecs.yorku.ca/course_archive/2014-15/F/2021/_media/labm.pdf
  • Fixed-Price – Est. Budget: $400.00 Posted
    Detailed Description is in the file attached. I want to secure the data and other critical security parameters present on FPGA. If an unauthorised user tries to temper the FPGA, all Critical Security parameters should be secured. Different methods are mentioned in the document like reset, ramoverwrite, etc. I might need you to implement 1 or 2 methods rather then all the methods mentioned in the document attached.
  • Fixed-Price – Est. Budget: $20.00 Posted
    design and comparison of 8bit risk and cisc processors. design a verilog code for risk and cisc processors running a set of 12 instructions and compare their timing analysis, their power dissipation and area. The instructions to be used are : add, addi, sub, subj, addc, subc, rol, ror, load wrd, store word, jump, subroutine, xor, xnor
  • Fixed-Price – Est. Budget: $5,000.00 Posted
    I have a source code it work in DE0 FPGA I need company have FPGA expert guy have in hands a more powerfull FPGA to run this code, bid telling what is the FPGA model you have that is the most powerfull
  • Fixed-Price – Est. Budget: $100.00 Posted
    Integrating two codes into one and implementing some extra features. Message me for more details.
  • Hourly – Posted
    I need someone to teach me how to design a pulse-width modulation (PWM) voltage controller for use with an FPGA. You can read about PWM here: http://en.wikipedia.org/wiki/Pulse-width_modulation I have a lot of programming experience in various languages like C, C++, MATLAB, etc., but none in Verilog. I need to design this controller for a SmartFusion ARM A2F500M3G chip. Therefore, I need to use a program called Libero. There is sample PWM design code available at ...
  • Hourly – 1 to 3 months – 10-30 hrs/week – Posted
    We are looking for VHDL developer to join our team. Our first task is to write an optimized Integer devider for Xilinx FPGA.
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