Est. Budget: $20.00
design and comparison of 8bit risk and cisc processors. design a verilog code for risk and cisc processors running a set of 12 instructions and compare their timing analysis, their power dissipation and area.
The instructions to be used are :
add, addi, sub, subj, addc, subc, rol, ror, load wrd, store word, jump, subroutine, xor, xnor