Verilog / VHDL Jobs

6 were found based on your criteria

  • Fixed-Price – Est. Budget: $50.00 Posted
    need to design a 16 bit pre-computation based content addressable memory using gate block selection algorithm.if you are ready to do the job and it has to be done in 3-4 hours.i can take care of the test bench.i need the verily code working properly and i can give complete details of the gate block selection algorithm.
  • Fixed-Price – Est. Budget: $1,000.00 Posted
    Want to share your experience using VLSI/Verilog with people that want to learn it? If you can make screen capture video tutorials showing how to use these topics from the basics to the advanced skills, you will love making an ONLINE COURSE with me! All you have to do is screen capture yourself using these programs and explaining what you already know how to do with it! Here are the basic project goals. 1) 20 to 50 screen capture ...
  • Fixed-Price – Est. Budget: $85.00 Posted
    The Basic aim of the project is to Design and implement a Hardware Firewall which would enable us to secure our Network.The hardware firewall will be packet filtering to examine the header of a packet to determine its source and desitination. The information will be compared to a set of predefined or user-created rules that determines whether the packet is to be forwarded or dropped. this has to be done using Xilinx Virtex-5 FPGA board using Verilog HDL
  • Fixed-Price – Est. Budget: $100.00 Posted
    Goal of the proposed iris recognition is to recognize human identity througb the textural characteristics of one's iris muscular patterns. Even though eye color is dependent on heredity, in contrast to this, iris is independent and uncorrelated even for twins. Out of various biometrics such as f'mger and band geometry, face, ear and voice recognition, iris recognition has been acknowledged as one of the most accurate biometric modalities because of its high recognition rate. In this proposed iris ...
loading