23 were found based on your criteria

  • Fixed-Price – Est. Budget: $120.00 Posted
    given the vhdl code it has to be implemented on virtex 5 borad first task is to explain me about the board second to implement on it and finally helping me to check the results by implementing it on board
  • Fixed-Price – Est. Budget: $100.00 Posted
    writing the semivariogram code in vhdl description of the topic will be provided and explained
  • Fixed-Price – Est. Budget: $100.00 Posted
    I need a freelancer who is proficient in VHDL. This for a school prject. Please be available to talk over skype, i will give material as well, once price is agreed upon.
  • Fixed-Price – Est. Budget: $2,000.00 Posted
    DfR Solutions, LLC is seeking a talented, self-driven and motivated software engineer/FPGA designer/engineer to support the development of a test to prove out the reliability of space-bound FPGA designs. The applicant must be proficient in Xilinx Vivado and ISE suites (specifically ISE WebPack design software from Xilinx) and technically confident to develop code while working independently. The objective of this contract is to develop an FPGA level software routine similar to an iterative Built-In-Self-Test (BIST) to be used ...
  • Hourly – Less than 1 month – Less than 10 hrs/week – Posted
    My team and I are developing a brand new FPGA. We need to know what kind of circuit designs we need to implement so that we can program the device easily. Altera Quartus II seems like a great software package for this type of chip programming. There are two major methods used by Quatus to program an FPGA: JTAG programming (volatile) and Active Serial programming (non-volatile). We need to know more details about these methods. First, describe the method of ...
  • Fixed-Price – Est. Budget: $60.00 Posted
    2 Directions design an MMP circuit showing the implemention of the two's complement multiplication algorithm from Project 1. No pseudo-instructions are al-lowed in the implementation. With the exception of the Control Unit, you may use only the com-ponents provided in the TinyCad symbol library|\gen_CompArch.TCLib". Initialize the Data Memory with the ASCII codes representing the multiplier and multiplicand numerals. Finally, design and simulate the MMP using hardware description language. Assume that the address of the rst instruction in ...
  • Hourly – 1 to 3 months – 10-30 hrs/week – Posted
    To develop and maintain our website. Adding new product category's-deleting old ones. Updating website. Must be able to write code for open cart. Must possess good understanding of html. Must communicate effectively.
  • Fixed-Price – Est. Budget: $45.00 Posted
    To complete the third and final phase of assembling FIR filter elements designed in phases 1 and 2. In phase 1 parametrizable Ripple Carry Adder was designed in VHDL and in phase 2 a design was made for a simple parametrizable State-Store for the FIR Filter in FPGA Advantage with Input data width of 10 bits coming from the A/D Converter. The multipliers to be used are those provided in the IEEE std-logic 1164 libraries, and available on the ...