Est. Budget: $45.00
To complete the third and final phase of assembling FIR filter elements designed in phases 1 and 2.
In phase 1 parametrizable Ripple Carry Adder was designed in VHDL and in phase 2 a design was made for a simple parametrizable State-Store for the FIR Filter in FPGA Advantage with Input data width of 10 bits coming from the A/D Converter.
The multipliers to be used are those provided in the IEEE std-logic 1164 libraries, and available on the ...