Stratix IV algorithm implementation

Stratix IV algorithm implementation

Cancelled

Job Description

I have an algorithm written for a DE0 FPGA board and then only translated to a DE4 FPGA board without using all the processing capacity of the DE4. I need someone to make changes on the codes so that all the logic capacity of processing of the board is used.

Please, let me know if you can do it and if you have any further question.

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