Modelsim & Xilinx expertise needed for a Verilog-Hdl project
Closed - This job posting has been filled and work has been completed.
We are working in a project , which we have done the code writing .When we run the code in Xilinx (without Test-bench part) it synthesized perfectly & shows the circuit diagram. But when we run the code in Modelsim , it shows compile & simulate done , but when we seen the waveform of Test-bench it shows some unknown value , & instead of that we saw the input output value as ZZZ or xxx or zzx value.(u need to synthesize the all code without the Test-bench in Xilinx then u will see the circuit. after that u have to compile & simulate the whole code in Modelsim & see the unknown result of Test-Bench).
For your reference i here attached the full coding here (Along with its paper (pdf part)).
We need the Code with its full functionality As early as possible (the code should run with error free & it gives us the perfect result), as it described in the paper (pdf file).
It is better if you suggest us about the budget , and the time you need to resolved the full Project.
N.B :: In the Paper (publication of PDF file )The code starts from Page 122 , the Testbench is in VHDL code format , we convert it in Verilog-HDL code with the help of X-HDL(translator) .
For compile & Simulate we are using "" ModelSim-Altera 6.5b (Quartus II 9.1) Starter Edition""
& For Synthesize we are using ""Xilinx ISE 9.2i ""
We need some help badly who is expertise in Modelsim & Xilinx, who can help us to solve the problem to get the waveform result in proper format.
Hope to hear from you soon .
Thanks in advance for your co-operation.
Thanks & Best Regards
Kamrul Hasan Shajib & Gazi Fuad Hasan