FPGA-based system for sending packets at accurate times
We want to use an FPGA-based system to send packets onto a network at very accurate times.
The system will get packet contents, along with a multicast group and a time, and it needs to send that packet on the multicast group within 50 microseconds of the specified time (within 10 microseconds would be preferable). At any given time, the system will have a number of packets waiting for their delivery time. There could be a number of different packets waiting for delivery at the same time, in which case one of the packets has to be delivered within 50 microseconds of the scheduled time, and the rest follow as soon as possible thereafter.
The system should use PTP to synchronize its local clock to a network clock.
A central server, not part of this project, will add packets to, and possibly remove packets from, the device. When the device boots, it should prompt the central server to provide it with packets waiting to be queued.
The device to be constructed for this project should interact over the network to
- Add a message to the queue
- Remove a message from the queue
- Provide a list of what is in the queue
- Keep a timestamped log someplace where it can be retrieved.
It should use DHCP to pick up addressing information.
We have a hardware platform that uses an Altera Cyclone IV chip, and which has both copper gigabit Ethernet and an SFP socket wired to the chip. The system can use either or both sockets, and it would be fine for device control go over the copper port, and use the SFP for sending out the packets.
I expect that the system will use a program running on a soft processor on the FPGA to interact with the outside world (add, remove, etc.) and use the FPGA to implement a hardware clock with PTP synchronization and the packet sending mechanism which uses that clock.
If you are interested in this job, please tell me why your background makes you a good choice.